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| tmp91fy12a 2001-08-31 91fy12a-1 cmos 16-bit microcontrollers TMP91FY12AF 1. outline and features TMP91FY12AF is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. TMP91FY12AF comes in a 100-pin flat package. listed below are the features. (1) high-speed 16-bit cpu (900/l1 cpu) ? instruction mnemonics are upward-compatible with tlcs-90/900 ? 16 mbytes of linear address space ? general-purpose registers and register banks ? 16-bit multiplication and division instructions; bit transfer and arithmetic instructions ? micro dma: 4 channels (1.0 s/2 bytes at 16 mhz) (2) minimum instruction execution time: 148 ns (at 27 mhz) (3) built-in ram: 4 kbytes built-in rom: 256 kbytes flash memory 2 kbytes mask rom (used for booting) (4) external memory expansion ? expandable up to 16 mbytes (shared program/data area) ? can simultaneously support 8-/16-bit width external data bus dynamic data bus sizing (5) 8-bit timers: 8 channels (6) 16-bit timer/event counter: 2 channels (7) general-purpose serial interface: 2 channels ? uart/synchronous mode: 2 channels ? irda ver 1.0 (115.2 kbps) supported: 1 channel purchase of toshiba i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as define d by philips. ? for a discussion of how the reliability of microcontrollers can be predicted, please refer to section 1.3 of the chapter entit led qualit y and reliability assurance / handling precautions. ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibi lity of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to a void situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage t o property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the mos t recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the handling gui de fo r semiconductor devices, or toshiba semiconductor reliability handbook etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfun ction or failure of which may cause loss of human life or bodily injury (unintended usage). unintended usage include atomic energy con trol instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control inst ruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be m ade at the customers own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assum ed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from i ts use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation o r others. ? the information contained herein is subject to change without notice. 000707 ebp1
tmp91fy12a 2001-08-31 91fy12a-2 (8) serial bus interface: 1 channel ? i 2 c bus mode/clock synchronous select mode (9) 10-bit ad converter (sample-hold circuit is built in): 8 channels (10) watchdog timer (11) timer for real-time clock (rtc) (12) chip select/wait controller: 4 channels (13) interrupts: 45 interrupts ? 9 cpu interrupts: software interrupt instruction and illegal instruction ? 26 internal interrupts: 7-level priority can be set. ? 10 external interrupts: 7-level priority can be set. (14) input/output ports: 81 pins (15) standby function three halt modes: idle2 (programmable), idle1, stop (16) triple-clock controller ? clock doubler (dfm) ? clock gear (fc to fc/16) ? slow mode (fs = 32.768 khz) (17) operating voltage ? v cc = 2.7 v to 3.6 v (fc max = 27 mhz) (18) package ? 100-pin qfp: p-qfp100-1414-0.50e tmp91fy12a 2001-08-31 91fy12a-3 4-kb ram 256-kb flash e 2 prom cpu (tlcs-900/l1) pc 10-bit 8ch ad converter h-osc sio/uart/irda (sio0) 8-bit timer (tmra0) port 0 32 bits f sr xwa xbc xde xhl xix xiy xiz xsp w a ix iy iz sp txd0 (p90) rxd0 (p91) txd1 (p93) rxd1 (p94) ta0in (p70) dvcc [3] dvss [3] x1 x2 (p00 to p07) ad0 to ad7 (p10 to p17) ad8/a8 to ad15/a15 (p20 to p27) a0/a16 to a7/a23 an0 to an7 (p50 to p57) avcc, avss vrefh, vrefl xt1 (p96) xt2 (p97) reset am0 am1 ale watch-dog timer (wdt) clock gear clock doubler sio/uart (sio1) serial bus interface ( sbi ) sck (p60) so/sda (p61) si / scl (p62) rd (p30) wr (p31) hwr (p32) busrq (p34) busak (p35) w r/ (p36) p37 ( boot ) l-osc emu0 emu1 port 3 (p64) scout, p65, p66 pa4 to pa7 cs/wait controller (4-block) port 1 port 2 port 6 port a real-clock timer (rtc) wait ( p33 ) cs0 to cs3 interrupt controller int0 (p64) int1 to 4 (pa0 to 3) 16-bit timer (tmrb0) tb0in0/int5 (p80) tb0in1/int6 (p81) tb0out0 (p82) tb0out1 (p83) 16-bit timer (tmrb1) tb1in0/int7 (p84) tb1in1/int8 (p85) tb1out0 (p86) tb1out1 (p87) 8-bit timer (tmra1) ta1out (p71) 8-bit timer (tmra2) 8-bit timer (tmra3) ta3out (p72) 8-bit timer (tmra4) ta4in (p73) 8-bit timer (tmra5) ta5out (p74) 8-bit timer (tmra6) 8-bit timer (tmra7) ta7out (p75) ( ): initial function after reset b c d e h l adtrg (p53) sclk0/ 0 cts (p92) sclk1/ cts1 (p95) (p40 to p43) nmi 2-kb boot rom figure 1.1 TMP91FY12AF block diagram tmp91fy12a 2001-08-31 91fy12a-4 2. pin assignment and pin functions the assignment of input/output pins for the TMP91FY12AF, their names and functions are as follows: 2.1 pin assignment diagram figure 2.1.1 shows the pin assignment of the TMP91FY12AF. dvss 91 p66 90 85 p62/si/scl 86 p63/int0 87 p64/scout 88 p65 dvcc 89 p52/an2 94 p51/an1 93 p50/an0 92 p55/an5 97 p54/an4 96 p53/an3/adtrg 95 vrefh 100 p57/an7 99 p56/an6 98 avcc 3 avss 2 top view qfp100 vrefl 1 p72/ta3out 6 p71/ta1out 5 p70/ta0in 4 p75/ta7out 9 p74/ta5out 8 p73/ta4in 7 p82/tb0out0 12 p81/tb0in1/int6 11 p80/tb0in0/int5 10 p85/tb1in1/int8 15 p84/tb1in0/int7 14 p83/tb0out1 13 p90/txd0 18 p87/tb1out1 17 p86/tb1out0 16 p93/txd1 21 p92/sclk0/cts0 20 p91/rxd0 19 dvcc 25 am0 24 p95/sclk1/cts1 23 p94/rx1 22 x2 26 am1 29 x1 28 dvss 27 p97/xt2 32 p96/xt1 31 reset 30 pa2/int3 37 pa1/int2 36 pa0/int1 35 emu1 34 emu0 33 81 p42/cs2 82 p43/cs3 83 p60/sck 84 p61/so/sda 80 p41/cs1 76 p35/busak 77 p36/r/w 78 p37/boot 79 p40/cs0 72 p31/wr 73 p32/hwr 74 p33/wait 75 p34/busrq 68 p25/a5/a21 69 p26/a6/a22 70 p27/a7/a23 71 p30/rd 64 dvcc 65 p22/a2/a18 66 p23/a3/a19 67 p24/a4/a20 60 p20/a0/a16 61 p21/a1/a17 62 dvss 63 nmi 58 p16/ad14/a14 59 p17/ad15/a15 54 p12/ad10/a10 55 p13/ad11/a11 56 p14/ad12/a12 57 p15/ad13/a13 49 p05/ad5 48 p04/ad4 50 p06/ad6 51 p07/ad7 52 p10/ad8/a8 53 p11/ad9/a9 46 p02/ad2 45 p01/ad1 47 p03/ad3 43 ale 42 pa7 44 p00/ad0 40 pa5 38 pa3/int4 39 pa4 41 pa6 figure 2.1.1 pin assignment diagram (100-pin qfp) tmp91fy12a 2001-08-31 91fy12a-5 2.2 pin names and functions the names of the input/output pins and their functions are described below. table 2.2.1 pin names and functions. table 2.2.1 pin names and functions (1/3) pin name number of pins i/o functions p00 to p07 ad0 to ad7 8 i/o tri-state port 0: i/o port that allows i/o to be selected at the bit level address and data (lower): bits 0 to 7 of address and data bus p10 to p17 ad8 to ad15 a8 to a15 8 i/o tri-state output port 1: i/o port that allows i/o to be selected at the bit level address and data (upper): bits 8 to 15 for address and data bus address: bits 8 to 15 of address bus p20 to p27 a0 to a7 a16 to a23 8 i/o output output port 2: i/o port that allows i/o to be selected at the bit level (with pull-down resistor) address: bits 0 to 7 of address bus address: bits 16 to 23 of address bus p30 rd 1 output output port 30: output port read: strobe signal for reading external memory p31 wr 1 output output port 31: output port write: strobe signal for writing data to pins ad0 to ad7 p32 hwr 1 i/o output port 32: i/o port (with pull-up resistor) high write: strobe signal for writing data to pins ad8 to ad15 p33 wait 1 i/o input port 33: i/o port (with pull-up resistor) wait: pin used to request cpu bus wait p34 busrq 1 i/o input port 34: i/o port (with pull-up resistor) bus request: signal used to request bus release p35 busak 1 i/o output port 35: i/o port (with pull-up resistor) bus acknowledge: signal used to acknowledge bus release p36 r/ w 1 i/o output port 36: i/o port (with pull-up resistor) read/write: 1 represents read or dummy cycle; 0 represents write cycle. p37 boot 1 i/o input port 37: i/o port (with pull-up resistor) this pin sets single boot mode. p40 cs0 1 i/o output port 40: i/o port (with pull-up resistor) chip select 0: outputs 0 when address is within specified address area p41 cs1 1 i/o output port 41: i/o port (with pull-up resistor) chip select 1: outputs 0 if address is within specified address area p42 cs2 1 i/o output port 42: i/o port (with pull-up resistor) chip select 2: outputs 0 if address is within specified address area p43 cs3 1 i/o output port 43: i/o port (with pull-up resistor) chip select 3: outputs 0 if address is within specified address area p50 to p57 an0 to an7 adtrg 8 input input input port 5: pin used to input port analog input: pin used to input to ad converter ad trigger: signal used to request start of ad converter p60 sck 1 i/o i/o port 60: i/o port serial bus interface clock in sio mode p61 so sda 1 i/o output i/o port 61: i/o port serial bus interface output data in sio mode serial bus interface data in i 2 c bus mode p62 si scl 1 i/o input i/o port 62: i/o port serial bus interface input data in sio mode serial bus interface clock in i 2 c bus mode p63 int0 1 i/o input port 63: i/o port interrupt request pin 0: interrupt request pin with programmable level / rising edge / falling edge p64 scout 1 i/o output port 64: i/o port system clock output: outputs f fph or fs clock. tmp91fy12a 2001-08-31 91fy12a-6 table 2.2.1 pin names and functions (2/3) pin name number of pins i/o functions p65 1 i/o port 65: i/o port p66 1 i/o port 66: i/o port p70 ta0in 1 i/o input port 70: i/o port timer a0 input p71 ta1out 1 i/o output port 71: i/o port timer a1 output p72 ta3out 1 i/o output port 72: i/o port timer a3 output p73 ta4in 1 i/o input port 73: i/o port timer a4 input p74 ta5out 1 i/o output port 74: i/o port timer a5 output p75 ta7out 1 i/o output port 75: i/o port timer a7 output p80 tb0in0 int5 1 i/o input input port 80: i/o port timer b0 input 0 interrupt request pin 5: interrupt request pin with programmable rising edge / falling edge. p81 tb0in1 int6 1 i/o input input port 81: i/o port timer b0 input 1 interrupt request pin 6: interrupt request on rising edge p82 tb0out0 1 i/o output port 82: i/o port timer b0 output 0 p83 tb0out1 1 i/o output port 83: i/o port timer b0 output 1 p84 tb1in0 int7 1 i/o input input port 84: i/o port timer b1 input 0 interrupt request pin 7: interrupt request pin with programmable rising edge / falling edge. p85 tb1in1 int8 1 i/o input input port 85: i/o port timer b1 input 1 interrupt request pin 8: interrupt request on rising edge p86 tb1out0 1 i/o output port 86: i/o port timer b1 output 0 p87 tb1out1 1 i/o output port 87: i/o port timer b1 output 1 p90 txd0 1 i/o output port 90: i/o port serial send data 0 (programmable open-drain) p91 rxd0 1 i/o input port 91: i/o port serial receive data 0 p92 sclk0 cts0 1 i/o i/o input port 92: i/o port serial clock i/o 0 serial data send enable 0 (clear to send) p93 txd1 1 i/o output port 93: i/o port serial send data 1 (programmable open-drain) p94 rxd1 1 i/o input port 94: i/o port (with pull-up resistor) serial receive data 1 p95 sclk1 cts1 1 i/o i/o input port 95: i/o port (with pull-up resistor) serial clock i/o 1 serial data send enable 1 (clear to send) p96 xt1 1 i/o input port 96: i/o port (open-drain output) low-frequency oscillator connection pin tmp91fy12a 2001-08-31 91fy12a-7 table 2.2.1 pin names and functions (3/3) pin name number of pins i/o functions p97 xt2 1 i/o output port 97: i/o port (open-drain output) low-frequency oscillator connection pin pa0 to pa3 int1 to int4 4 i/o input ports a0 to a3: i/o ports interrupt request pins 1 to 4: interrupt request pins with programmable rising edge / falling edge. pa4 to pa7 4 i/o ports a4 to a7: i/o ports ale 1 output address latch enable can be disabled to reduce noise. nmi 1 input non-maskable interrupt request pin: interrupt request pin with programmable falling edge or both edge. am0 to 1 2 input address mode: the vcc pin should be connected. emu0/emu1 1 output test pins: open pins reset 1 input reset: initializes tmp91fy12a. (with pull-up resistor) vrefh 1 input pin for reference voltage input to ad converter (h) vrefl 1 input pin for reference voltage input to ad converter (l) avcc 1 i/o high-frequency oscillator connection pins avss 1 power supply pin for ad converter x1/x2 2 gnd pin for ad converter (0 v) dvcc 3 power supply pins (all vcc pins should be connected with the power supply pin.) dvss 3 gnd pins (0 v) (all vss pins should be connected with the power supply pin.) note: an external dma controller cannot access the devices built-in memory or built-in i/o devices using the busrq and busak signal. tmp91fy12a 2001-08-31 91fy12a-8 3. functional description this section shows the hardware configuration of the tmp91fy12a and explains how it operates. this device is a version of the created by replacing the predecessor?s internal mask rom with a 256-kbyte internal flash memory. the configuration and the functionality of this device are the same as those of the tmp91cw12a. for the functions of this device that are not described here, refer to the tmp91cw12a data sheet. 3.1 outline of operation modes there are single-chip and single-boot modes. which mode is selected depends on the device?s pin state after a reset (including when the watchdog timer output is connected to reset (inside the chip)). ? single chip mode: the device normally operates in this mode. after a reset, the device starts executing the internal flash memory program. ? single boot mode: this mode is used to rewrite the internal flash memory by serial transfer (uart). after a reset, the internal boot rom starts up, executing a on-board rewrite program. table 3.1.1 operation mode setup table mode setup input pin operation mode reset boot (p37) am0 am1 single-chip mode h single-boot mode l hh tmp91fy12a 2001-08-31 91fy12a-9 3.2 memory map the memory map of this device differs from that of the tmp91cw12a. figure 3.2.1 shows a memory map of the device in single-chip mode and its memory areas that can be accessed in each addressing mode of the cpu. 000000h 001000h 16-mbyte area (r) ( ? r) (r + ) (r + r8/16) (r + d8/16) (nnn) direct area (n) 64-kbyte area (nn) internal rom (256 kbytes) internal i/o (4 kbytes) internal ram (4 kbytes) 002000h 010000h fc0000h ( = internal area) ffff00h ffffffh vector table (256 bytes) external memory 000100h figure 3.2.1 memory map (single-chip mode) tmp91fy12a 2001-08-31 91fy12a-45 4. electrical characteristics 4.1 absolute maximum ratings parameter symbol rating unit power supply voltage vcc ? 0.5 to 4.0 v input voltage vin ? 0.5 to vcc + 0.5 v output current iol 2 ma output current ioh ? 2ma output current (total) iol 80 ma output current (total) ioh ? 80 ma power dissipation (ta = 85c) pd 600 mw soldering temperature (10 s) tsolder 260 c storage temperature tstg ? 65 to 150 c operating temperature topr ? 20 to 70 c number of times program erase n ew 10000 cycle note: the absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. tmp91fy12a 2001-08-31 91fy12a-46 4.2 dc characteristics (1/2) parameter symbol condition min typ. (note 1) max unit power supply voltage (avcc = dvcc) (avss = dvss = 0 v) v cc fc = 4 to 27 mhz fs = 30 to 34 khz 2.7 3.6 v p00 to p17 (ad0 to 15) v il vcc = 2.7 to 3.6 v 0.6 p20 to pa7 (except p63) v il1 vcc = 2.7 to 3.6 v 0.3 vcc reset , nmi , p63 (int0) v il2 vcc = 2.7 to 3.6 v 0.25 vcc am0, 1 v il3 vcc = 2.7 to 3.6 v 0.3 input low volta g e x1 v il4 vcc = 2.7 to 3.6 v ? 0.3 0.2 vcc p00 to p17 (ad0 to 15) v ih vcc = 2.7 to 3.6 v 2.0 p20 to pa7 (except p63) v ih1 vcc = 2.7 to 3.6 v 0.7 vcc reset , nmi , p63 (int0) v ih2 vcc = 2.7 to 3.6 v 0.75 vcc am0, 1 v ih3 vcc = 2.7 to 3.6 v vcc ? 0.3 input hi g h volta g e x1 v ih4 vcc = 2.7 to 3.6 v 0.8 vcc vcc + 0.3 v output low voltage v ol iol = 1.6 ma vcc = 2.7 to 3.6 v 0.45 output high voltage v oh ioh = ? 400 avcc = 2.7 to 3.6 v 2.4 v note 1: typical values are for when ta = 25c and vcc = 3.0 v unless otherwise noted. tmp91fy12a 2001-08-31 91fy12a-47 4.2 dc characteristics (2/2) parameter symbol condition min typ. (note 1) max unit input leakage current) ili 0.0 v in vcc 0.02 5 output leakage current ilo 0.2 v in vcc ? 0.2 0.05 10 a power down voltage (at stop, ram back-up) vstop v il2 = 0.2 vcc, v ih2 = 0.8 vcc 2.7 3.6 v reset pull-up resistor rrst vcc = 3 v 10% 100 400 k ? pin capacitance cio fc = 1 mhz 10 pf schmitt width reset , nmi , int0 vth vcc = 2.7 to 3.6 v 0.4 1.0 v programmable pull-up resistor rkh vcc = 3 v 10% 100 400 k ? normal (note 2) 30.0 45.0 idle2 4.5 7.0 idle1 vcc = 3 v 10% fc = 27 mhz 2.0 4.0 ma slow (note 2) 30.0 40 idle2 9.0 25 idle1 vcc = 3 v 10% fs = 32.768 khz 6.0 15 a stop icc vcc = 3 v 10% 1.0 15 a note 1: typical values are for when ta = 25c and vcc = 3.0 v unless otherwise noted. note 2: icc measurement conditions (normal, slow): all functions are operating; output pins are open and input pins are fixed. tmp91fy12a 2001-08-31 91fy12a-48 4.3 ac characteristics (1) vcc = 3.0 v 10% variable f fph = 27 mhz no. parameter symbol min max min max 1 f fph period ( = x) t fph 37.0 31250 37.0 ns 2 a0 to a15 vaild ale fall t al 0.5x ? 6 12 ns 3 ale fall a0 to a15 holdt la 0.5x ? 16 2 ns 4 ale high width t ll x ? 20 17 ns 5 ale fall rd / wr fall t lc 0.5x ? 14 4 ns 6 rd rise ale rise t clr 0.5x ? 10 8 ns 7 wr rise ale rise t clw x ? 10 27 ns 8 a0 to a15 valid rd / wr fall t acl x ? 23 14 ns 9 a0 to a23 valid rd / wr fall t ach 1.5x ? 26 29 ns 10 rd rise a0 to a23 hold t car 0.5x ? 13 5 ns 11 wr rise a0 to a23 hold t caw x ? 13 24 ns 12 a0 to a15 valid d0 to d15 input t adl 3.0x ? 38 73 ns 13 a0 to a23 valid d0 to d15 input t adh 3.5x ? 41 88 ns 14 rd fall d0 to d15 input t rd 2.0x ? 30 44 ns 15 rd low width t rr 2.0x ? 15 59 ns 16 rd rise d0 to a15 hold t hr 00ns 17 rd rise a0 to a15 output t rae x ? 15 22 ns 18 wr low width t ww 1.5x ? 15 40 ns 19 d0 to d15 valid wr rise t dw 1.5x ? 35 20 ns 20 wr rise d0 to d15 hold t wd x ? 25 12 ns 21 a0 to a23 valid wait input t awh 3.5x ? 60 69 ns 22 a0 to a15 valid wait input t awl 3.0x ? 50 61 ns 23 rd / wr fall wait hold t cw 2.0x + 0 74 ns 24 a0 to a23 valid port input t aph 3.5x ? 89 40 ns 25 a0 to a23 valid port holdt aph2 3.5x 129 ns 26 a0 to a23 valid port valid t ap 3.5x + 80 209 ns ac measuring conditions ? output level: high = 0.7 vcc, low = 0.3 vcc, cl = 50 pf ? input level: high = 0.9 vcc, low = 0.1 vcc note: x used in an expression shows a frequency for the clock f fph selected by syscr1 tmp91fy12a 2001-08-31 91fy12a-49 (2) raed cycle t hr t acl f fph a0 to a23 r/ w port input rd ad0 to ad15 ale t fph t awh t awl t aph a0 to a15 t adh t ll t al t la t ach t lc t rr t car t rae t clr d0 to d15 t cw t aph2 t adl cs0 to cs3 wait t rd tmp91fy12a 2001-08-31 91fy12a-50 (3) write cycle a0 to 15 d0 to 15 t wd t ap t ww t dw f fph a0 to 23 r/ w port output ad0 to 15 ale wait wr , hwr cs0 to cs3 t caw t clw tmp91fy12a 2001-08-31 91fy12a-51 4.4 ad conversion characteristics avcc = vcc, avss = vss parameter symbol condition min typ. max unit analog reference voltage ( + ) vrefh v cc = 3 v 10% v cc ? 0.2 v v cc v cc analog reference voltage ( ? ) vrefl v cc = 3 v 10% v ss v ss v ss + 0.2 v analog input voltage range vain v refl v refh v analog current for analog reference voltage tmp91fy12a 2001-08-31 91fy12a-52 4.5 serial channel timing (i/o internal mode) (1) sclk input mode variable 10 mhz 27 mhz parameter symbol min max min max min max unit sclk period t scy 16x 1.6 0.59 s output data sclk rising /falling edge (note) t oss t scy /2 ? 4x-110 290 38 ns sclk rising/falling edge (note) output data hold t ohs t scy /2 + 2x + 0 1000 370 ns sclk rising/falling edge (note) input data hold t hsr 3x + 10 310 121 ns sclk rising/falling edge (note) valid data input t srd t scy ? 0 1600 592 ns valid data inputsclk rising/falling edge (note) t rds 000ns note : sclk rinsing/falling edge: the rising edge is used in sclk rising mode. the falling edge is used in sclk falling mode. (2) sclk output mode variable 10 mhz 27 mhz parameter symbol min max min max min max unit sclk period (programable) t scy 16x 8192x 1.6 819 0.59 303 s output data sclk rising edge t oss t scy /2 ? 40 760 256 ns sclk rising edge output data hold t ohs t scy /2 ? 40 760 256 ns sclk rising edge input data holdt hsr 000ns sclk rising edge valid data input t srd t scy ? 1x ? 180 1320 375 ns valid data input sclk rising edge t rds 1x + 180 280 217 ns t srd t hsr t scy output data txd sclk (input mode) sclk output mode/ input mode 0 t oss t ohs 13 01 3 2 2 valid input data rxd validvalidvalid t rds tmp91fy12a 2001-08-31 91fy12a-53 4.6 event counter (ta0in, ta4in, tb0in0, tb0in1, tb1in0, tb1in1) variable 10 mhz 27 mhz parameter symbol min max min max min max unit clock perildt vck 8x + 100 900 396 ns clock low level width t vckl 4x + 40 440 188 ns clock high level width t vckh 4x + 40 440 188 ns 4.7 interrupt and capture (1) nmi , int0 to int4 interrupts variable 10 mhz 27 mhz parameter symbol min max min max min max unit nmi , int0 to int4 low level width t intal 4x + 40 440 188 ns nmi , int0 to int4 high level width t intah 4x + 40 440 188 ns (2) int5 to int8 interrupts, capture the int5 to int8 input width depends on the system clock and prescaler clock settings. t intbl (int5 to int8 low level width) t intbh (int5 to int8 high level width) variable f fph = 27 mhz variable f fph = 27 mhz system clock selected tmp91fy12a 2001-08-31 91fy12a-54 4.9 bus request/bus acknowledge busak a0 to a23, rd , wr cs0 to cs3 , r/ w , hwr ale ad0 to ad15 t cbal t aba t baa (note 2) (note 2) (note 1) busrq variable f fph = 10 mhz f fph = 27 mhz paramter symbol min max min max min max condition unit output buffer off to busak low t aba 080 0 80 0 80vcc = 2.7 to 3.6 v ns busak high to output buffer on t baa 080 0 80 0 80vcc = 2.7 to 3.6 v ns note 1: even if the busrq signal goes low, the bus will not be released while the wait signal is low. the bus will only be released when busrq goes low while wait is high. note 2: this line shows only that the output buffer is in the off state. it does not indicate that the signal level is fixed. just after the bus is released, the signal level set before the bus was released is maintained dynamically by the external capacitance. therefore, to fix the signal level using an external resister during bus release, careful design is necessary, since fixing of the level is delayed. the internal programmable pull-up/pull-down resistor is switched between the active and non-active states by the internal signal. tmp91fy12a 2001-08-31 91fy12a-55 4.10 recommended oscillation circuit the TMP91FY12AF has been evaluated by the following resonator manufacturer. the evaluation results are shown below for your information. note: the load capacitance of the oscillation terminal is the sum of the load capacitances of c1 and c2 to be connected and the stray capacitance on the board. even if the ratings of c1 and c2 are used, the load capacitance varies with each board and the oscillator may malfunction. therefore, when designing a board, make the pattern around the oscillation circuit shortest. it is recommended that final evaluation of the resonator be performed on the board. (1) examples of resonator connection x1 c1 c2 x2 rd figure 4.10.1 high-frequency oscillator connection xt1 c1 c2 xt2 rd figure 4.10.2 low-frequency oscillator connection (2) recommended ceramic resonators for the TMP91FY12AF: murata manufacturing co., ltd. ta = ? 40 to 85 ` recommended rating item oscillation frequency [mhz] recommended resonator c1 [pf] c2 [pf] rd [k ? ] vcc [v] remarks 4.0 csts0400mg06 (47) (47) 6.75 csts0675mg06 (47) (47) csa12.5mtz 30 30 12.5 cst12.5mtw (30) (30) 20.0 csa20.00mxz040 7 7 csa27.00mxz040 5 5 high- frequency oscillator 27.0 cst27.00mxw040 (5) (5) 0 2.7 to 3.3 ? ? the values enclosed in brackets in the c1 and c2 columns apply to the condenser built-in type. ? the product numbers and specifications of the resonators by murata manufacturing co., ltd. are subject to change. for up-to-date information, please refer to the following url; http://www.murata.co.jp/search/index.html tmp91fy12a 2001-08-31 91fy12a-56 |
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